This event has ended. View the official site or create your own event → Check it out
This event has ended. Create your own
View analytic
Tuesday, March 28 • 15:55 - 16:35
Register Allocation and Instruction Scheduling in Unison

Sign up or log in to save this to your schedule and see who's attending!

This talk presents Unison - a simple, flexible and potentially optimal tool that solves register allocation and instruction scheduling simultaneously. Unison is integrated with LLVM's code generator and can be used as a complement to the existing heuristic algorithms.

The ability to deliver optimal code makes Unison a powerful tool for LLVM users and developers: LLVM users can trade compilation time for code quality beyond the usual -O{0,1,2,3,..} optimization levels; LLVM developers can identify improvement opportunities in the existing heuristic algorithms. The talk discusses some of the improvement opportunities identified so far with the help of Unison.

avatar for Roberto Castañeda Lozano

Roberto Castañeda Lozano

Swedish Institute of Computer Science (SICS) & KTH

Tuesday March 28, 2017 15:55 - 16:35
HS002, E1 3

Attendees (21)